1. Field of the Invention
This invention relates to processes for developing isolation walls in semiconductor devices such as integrated circuit (IC) chips. More particularly, this invention is related to so-called trench isolation, wherein a trench is formed in the semiconductor device and filled with an insulating material.
2. Description of the Prior Art
It frequently is necessary to electrically isolate adjacent portions of an integrated circuit, and various techniques have been developed for this purpose. One such technique that has practical advantages is that of forming a trench at the place where isolation is needed, and filling the trench with an insulating material. Although a variety of proposals have been put forward for such purpose, important problems have arisen with all of those proposals.
For example, when a field oxide is thermally grown over a trench isolation region, a large step can (with prior art techniques) develop in the field oxide just above the trench edge, due to the usual difference in height between the insulation surface and the surrounding silicon, and the commonly lower oxidation rate of the insulating material as compared to the surrounding bulk material. Another problem is that notches can develop in the field oxide if the trench filling is layered in such a way that differential etching occurs at one or more layers. Such notches can attract residues from subsequent layers deposited over the trench (to form portions of the integrated circuit) such that conductive lines crossing the trench become electrically inter-connected, thereby resulting in a defective part. Also, when using trench isolation with a Silicon On Insulation (SOI) substrate, the removal of the trench hard mask after trench etch can lead to unintended etching of the buried insulating layer which can cause defective parts.
Efforts have been made by others to solve some of these and still further problems. For example, it has been proposed to use a combination of additional oxide steps and a nitride/oxide sandwich layer, as described in U.S. Pat. No. 4,791,073. Such a procedure however is excessively complex. Moreover, the additional thermal steps can adversely affect the characteristics of the final product, and such procedure would not in any event solve the problem of etching of the buried oxide layer of a Silicon-On-Insulation substrate.